Pin assignment with global routing for general cell designs

In this paper, we present an algorithm which combines the pin assignment step and the global routing step in the physical design of VLSI circuits. Our algorithm is based on two key theorems: the channel pin assignment theorem and the block boundary decomposition theorem. These two theorems enable us to deal successfully with the high complexity resulting from combining the pin assignment and global routing steps. According to these two theorems, we only need to generate a coarse pin assignment and global routing solution. The exact pin locations and global routing topology can be determined optimally later by a linear time algorithm. We implemented a pin assignment and global routing package named BeauticianGR based on the proposed algorithm. BeauticianGR produces very satisfactory results on test circuits and is being integrated into the automatic layout design system at the National Semiconductor Corporation.